BCM8154 ? multirate low-power 10g nrz/duobin ary transceiver with 10g clock ? fully integrated multirate cdr, demux, mux, cmu ? 300-pin multisource agreement (msa) compatible ? compliant to itu gr-253, xfp, and sfp+ specifications ? 16-bit lvds interface compliant to optical internetworking forum (oif) sfi-4 ? programmable nrz/duobinary modes ? rx equalization for isi compensation ? limiting amplifier ? rx phase adjustment ? adaptable rx decision threshold adjustment ? 10g serial transmit clock output with adjustable phase ? 10g serial tx preemphasis ? prbs generator/checker fo r built-in self-test (bist) ? line and system loopback modes ? receiver and transmitter serial data polarity inversion ? lvds polarity inversion and bit order reversal ? analog loss-of-signal output (alosb) and loss-of-signal input (losib) ? cmu and cdr lock detect ? fifo overflow alarm ? reference clock: 1/16 or 1/64 of the line data rate ? selectable rx clock and rx data squelch ? selectable timing modes/cleanup are field configurable ? internal phase detector and charge pump for cleanup phase- locked loop ( pll) (external vcxo required) ? broadcom serial control (bsc) interface compatible with philips ? i 2 c standard ? optional spi interface ? core voltage, 1v ? low-power: 650 mw ? compliant to oif, telcordia ? , itu-t, xfi specification, and ieee 802.3ae standards ? input sensitivity 10 mv peak-to-peak ? fault isolation with loopbacks, pattern generator, and checker ? reduces design cycle and time-to-market ? high-level of integration allows for higher port density solutions. ? lowest power sfi-4 to 10g serial transceiver ? standard cmos 65-nm fabrication process features summary of benefits ? oc-192/stm-64/10-gbe/fec transmission equipment ? sonet/sdh/10-gbe/10fc/fec for nrz or duobinary optical modules ? add/drop multiplexers ? digital cross-connects ? atm switch backbone ? sonet/sdh/10-gbe/10fc/fec for nrz, rz, or duobinary test equipment ? terabit and edge routers applications
overview ? phone: 949-926-5000 fax: 949-926-5203 e-mail: info@broadcom.com web: www.broadcom.com broadcom corporation 5300 california avenue, irvine, california 92617 ? 2008 by broadcom corporation. all rights reserved. 8154-pb01-r 02/14/08 broadcom ? , the pulse logo, connecting everything ? , and the connecting everything logo are among the trademarks of broadcom corporation and/or its aff iliates in the united states, certain other countries and/or the eu. any other trademarks or trade name s mentioned are the property of their respective owners. BCM8154 interface block diagram the BCM8154 is a fully integrated msa-compatible multirate sonet/ sdh/10-gbe/fibre-channel/fec transceiver operating at 9.953 gbps, 10.3125 gbps, 10.519 gbps, 10.664 gbps, 10.709 gbps, 11.095 gbps, 11.318 gbps, or 11.352 gbps. on-chip clock synthesis is performed by the high-frequency, low-jitter pll, allowing the use of a low-frequency reference clock selectable to the line rate divided by either 16 or 64. the 10g tx clock phase is adjustable for clocked driver applications. an on- chip phase detector and charge pump plus external vcxo implement a cleanup pll. the cleanup pll can be used to attenuate jitter on the cdr recovered clock for loop timing applications or to provide a low-jitter reference clock from a noisy system clock. any sonet timing mode may be configured with the new BCM8154 timing architecture, making the timing mode and cleanup functions user-selectable in the field rather than during manufacturing, therefore, simplifying engineering and manufacturing requirements. new features added to the BCM8154 include: ? prbs generator/checker for bist ? adaptive decision threshold adjustment ? adjustable 10g tx clock phase ? 10g rx equalization for isi compensation ? 10g tx preemphasis ? differential duobinary precoder ? bsc interface (compatible with philips i 2 c standard) or optional spi interface the low-jitter lvds interface guarantees compliance with the bit error rate requirements of the telcordia (formerly bellcore), ansi, and itu- t standards. the BCM8154 is offered in two different packages: 1. 15 mm x 15 mm, 301-pin bga compatible with the bcm8152 (0.8- mm ball pitch) 2. 15 mm x 15 mm, 196-pin bga (1-mm ball pitch) system interface line interface txrefclkp/n rxrefclkp/n vcxop/n txpclkp/n txmclkp/n rxmclkp/n txpiclkp/n txdin[15:0]p/n rxpoclkp/n rxdout[15:0]p/n tsdp/n tsclkp/n rdinp/n txvcp/n rxvcp/n offsetp/n phdout rdincm auxp/n rb_cal rb_cal_vss txfifoerrb txlockerrb phdlockerrb alosb rxfifoerrb rxlockerrb resetb losib txrefsel spi_sel sda scl adr[2:0] +1.0v +1.8v +3.3v vss +1.0v differential externally ac-coupled internally biased +1.0v differential cml externally ac-coupled internally biased +1.0v lvds +1.0v lvds +1.8v/2.3v lvds +1.0v differential cml externally ac-coupled +1.0v differential cml externally ac-coupled internally biased +1.0v analog +3.3v analog connect 4.75-k resistor between these two pins +3.3v cmos +3.3v cmos open drain cmos reference clock inputs reference clock outputs transmitter parallel inputs receiver parallel outputs filter and bias inputs clean-up pll charge pump output resistor calibration reference status outputs control inputs bsc transmit serial outputs receive serial input auxillary input bypass
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